The high frequency characterization measurements, performed on various active and passive electronic devices, semiconductor devices and integrated circuits thereof prepared on a wafer made of silicon and other semiconductor materials, are the basis for device modeling and model parameter extraction and circuit design and evaluation. This high frequency characterization measurement, particularly the high frequency characterization measurement for model parameter extraction of devices, must correspond to specific ports of a device under test (DUT), the locations of which are precisely defined. For this reason, it is necessary to remove all the parasitics, added by instruments, cables, probes and on-wafer testing set-up required to perform the high frequency measurement, from the raw data of the measurement. This is known as the so-called calibration procedure which is a key technique for ensuring accurate extraction of model parameters of high frequency devices.
With regard to the on-wafer high frequency measurement, calibration in a broad sense consists of two steps: off-wafer calibration and on-wafer de-embedding. In the first step, by off-wafer calibration, a test reference plane is moved from vector network analyzer (VNA) to the tip of on-wafer high frequency testing probes by using a set of impendence standard substrate (ISS) calibration dummies (generally made of alumina ceramic substrate). Techniques usually adopted here include short-open-load-thru (SOLT), line-reflect-reflect-match (LRRM), thru-reflect-line (TRL), four-port method (16-term error model), and the like. In the second step, by on-wafer de-embedding, the test reference plane is further shifted to ports of the DUT by using a suite of on-wafer de-embedding dummies. In recent years, a general four-port on-wafer de-embedding method has been proposed to strip the related parasitics of on-wafer measurements. The physical basis of the so-called general four-port method is to describe all the parasitics between the tips of the probes and the ports of the DUT by including them in a general four-port network, the four ports of which are defined at the tips of the probes and the ports of the DUT, respectively. FIG. 1 is a schematic view of an on-wafer high frequency characterization measurement set-up, wherein input and output testing ports of the VNA configured to test S parameters of the DUT are connected through high frequency cables to input and output on-wafer high frequency testing probes, respectively. The tips of the said probes are made contact with the surfaces of input and output on-wafer probing pads, respectively, and the sad probing pads are connected through on-wafer input and output access lines to input and output terminals of the DUT, respectively. FIG. 2 is a schematic view of the corresponding general parasitic four-port network. Here, the tip of the input testing probe, the input terminal of the DUT, the output terminal of the DUT, and the tip of the output testing probe are defined as port 0, port 1, port 2 and port 3 of the said parasitic four-port network, respectively, and those ports are denoted by P0, P1, P2 and P3, respectively. The following equation (1) can be obtained through proper theoretical derivation:YM=Yee−Yei(YA+Yii)−1Yie  (1)where, YA denotes the Y-parameter 2×2 admittance matrix from P1 to P2, i.e., the intrinsic two-port Y-parameter 2×2 admittance matrix of the DUT; YM denotes the Y-parameter 2×2 admittance matrix from P0 to P3, i.e., the measured whole two-port Y-parameter 2×2 admittance matrix of the DUT including all the on-wafer parasitics; and Yee, Yii, Yei and Yie are four Y-parameter 2×2 admittance sub-matrices of the Y-parameter 4×4 admittance matrix for describing those parasitic four-port network characteristics. Equation (1) is transformed to Equation (2):YA=−Yii−Yie(YM−Yee)−1Yei  (2)As can be seen, YA as the left side of the Equation(2) can be obtained as long as that the right side of Equation (2) is known after the measured value of YM is substituted. That is, the intrinsic high frequency characterization measurement result YA of the DUT is obtained by stripping all the on-wafer parasitics from the raw data of the whole high frequency characterization measurement YM of the DUT, achieving the purpose of the high frequency characterization measurement de-embedding. Therefore, total 16 elements of the four Y-parameter 2×2 admittance matrices Yee, Yii, Yei and Yie for describing said parasitic four-port network need to be determined. A proper equation set, which is composed of equations obtained by applying Equation(1) to a sufficient number of on-wafer de-embedding dummies with both measured YM and theoretical YA known, can be solved for the said 16 matrix element. Accordingly, for the general four-port method, five two-port on-wafer de-embedding dummies are usually adopted, i.e., Open O, Short S, Left L, Right R, and Thru T, the equivalent circuits of which are shown in FIG. 3. where their corresponding intrinsic two-port Y-parameter admittance matrices are respectively:
                              Y          AO                =                  [                                                    0                                            0                                                                    0                                            0                                              ]                                    (        3        )                                          Y          AS                =                  [                                                    ∞                                            0                                                                    0                                            ∞                                              ]                                    (        4        )                                          Y          AL                =                              [                                                                                Y                    L                                                                    0                                                                              0                                                  0                                                      ]                    =                      [                                                                                                      G                      L                                        +                                          j                      ⁢                                                                                          ⁢                      ω                      ⁢                                                                                          ⁢                                              C                        L                                                                                                              0                                                                              0                                                  0                                                      ]                                              (        5        )                                          Y          AR                =                              [                                                            0                                                  0                                                                              0                                                                      Y                    R                                                                        ]                    =                      [                                                            0                                                  0                                                                              0                                                                                            G                      R                                        +                                          j                      ⁢                                                                                          ⁢                      ω                      ⁢                                                                                          ⁢                                              C                        R                                                                                                                  ]                                              (        6        )                                          Y          AT                =                  [                                                    s                                                              -                  t                                                                                                      -                  t                                                            s                                              ]                                    (        7        )            Respectively substituting Equations (3)-(7) into Equation (1) obtains an equation set formed of an enough number of equations. After solving said equation set, by using Equation (2), the intrinsic Y-parameter admittance matrix YA of the DUT can be calculated from the measured whole Y-parameter admittance matrix YM of the DUT, i.e., the high frequency de-embedding for stripping said on-wafer parasitics is completed. Specifically, if said parasitic four-port network is passive and contains no any anisotropic material, and further more specifically, if said parasitic four-port network is symmetrical, the number of such on-wafer de-embedding dummies may be decreased to four, even three, as needed. In this way, the complexity and workload of de-embedding related testing structure designs, wafer fabrication, testing and data processing can be effectively decreased.
As described above, said general four-port high frequency de-embedding method is to further shift the test reference planes to input and output ports of the DUT, respectively, on the basis of off-wafer calibration in which the test reference planes are moved from the VNA to the tips of the on-wafer testing probes by using a suite of ISS calibration dummies. Actually, said general four-port high frequency de-embedding method is also suitable for directly moving the test reference planes from VNA to input and output ports of the DUT, without requiring off-wafer calibration based on the ISS calibration dummies, and this is called one-step calibration method. However, in doing this, the premise is that it is necessary to change, in the general four-port network as shown in FIG. 2, the definition of location of P0 from the tip of the input testing probe to the input testing port of the VNA and the definition of location of P3 from the tip of the output testing probe to the output testing port of the VNA, while maintaining the definition of locations of P1 and P2 as the input terminal of the DUT and the output terminal of the DUT. It is to be declared here that the general four-port on-wafer high frequency de-embedding method involved in the present invention may be applicable to on-wafer de-embedding after the completion of off-wafer calibration based on the ISS calibration dummies, and also may be used, as the one-step calibration method, in on-wafer de-embedding which directly moves the high frequency test reference planes directly from VNA to the input and output ports of the DUT without requiring off-wafer calibration based on the ISS calibration dummies.
The general four-port high frequency de-embedding method has the following advantages: the starting points and end points, from and to which, respectively, the test input and output reference planes need to move, are defined as ports of a general four-port network, respectively, and in this way, all the on-wafer parasitics to be stripped in de-embedding are contained in said general four-port network, without making any assumptions on the specific form of the interior structure of said general four-port network containing all the parasitics, and hence, the universality of said de-embedding technique is ensured. However, a problem with the prior art of said general four-port high frequency de-embedding method is that idealized assumption is made on the network characteristics of the required two-port on-wafer de-embedding dummies, and those idealized on-wafer de-embedding dummies are actually unachievable in reality, and consequently, errors are inevitably introduced. Specifically, this is first manifested in Open and Short dummies. Referring to Equations (3) and (4), ideal Open requires y11=y22=0 for YAO and ideal Short requires y11=y22=∞(infinite) for YAS. Meanwhile, ideal Open and ideal Short further require that there is no any coupling between the input port and the output port, and hence, for both YAO and YAS, y12=y21=0. However, actually, on-wafer Open and Short dummies are non-ideal no matter how they are designed and fabricated. Due to the presence of parasitics (for example, parasitic resistances, parasitic capacitances, parasitic inductances or the like), the admittances (y11 and y22 of YAO) of the actual Open are not equal to 0 and the admittances (y11 and y22 of YAS) of the actual Short are not infinite, either, and also coupling inevitably exists between the input port and the output port of the actual Open and Short dummies, and hence, for both YAO and YAS, y12 and y21 are not strictly equal to 0, either. Secondly, with regard to the Left and Right dummies, the prior art of the general four-port high frequency de-embedding is implemented by connecting conductors GL and GR to the input port and the output port, respectively, on the basis of the Open dummy. Although, as shown in FIGS. 3 (c)-(d) and Equations (5) and (6), the prior art also takes into account parasitic capacitances CL and CR connected in parallel with GL and GR to form access admittances YL and YR of the Left and Right dummies, respectively, determined by the distributed nature of high frequency operation, particularly as the operating frequency is increased from radio frequency and microwave band to millimeter wave band, artificially-designed conductors (i.e., resistors) cannot, once fabricated on a wafer, be strictly and accurately described only by a simple lumped equivalent circuit having conductors (resistors) and capacitors connected in parallel. That is, forcibly setting y11 and y22 of YAC and YAR to be respectively equal to GL+jωCL and GR+jωCR does not accord with the fact. AgOn, since the Left and Right dummies are built based on the Open dummy, the non-ideal characteristic problem with the actual Open dummy as described above still exists here. As a result, simply zeroing y12, y21 and y22 of YAL and y11, y12 and y21 of YAR in Equations (5) and (6), respectively, inevitably causes corresponding errors.